Verilog HDL

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Verilog HDL
A guide to Digital Design and Synthesis
By Samir Palnitkar


Table of Contents 

PART 1 BASIC VERILOG TOPICS

1 Overview of Digital Design with Verilog HDL

2 Hierarchical Modeling Concepts

3 Basic Concepts

4 Modules and Ports

5 Gate-Level Modeling

6 Dataflow Modeling

7 Behavioral Modeling

8 Tasks and Functions

9 Useful Modeling Techniques

PART 2 Advance Verilog Topics

10 Timing and Delays

11 Switch- Level Modeling

12 User-Defined Primitives

13 Programming Language Interface

14 Logic Synthesis with Verilog HDL



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